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general description the max5003 high-voltage switching power-supplycontroller has all the features and building blocks need- ed for a cost-effective flyback and forward voltage- mode control converter. this device can be used to design both isolated and nonisolated power supplies with multiple output voltages that operate from a wide range of voltage sources. it includes a high-voltage internal start-up circuit that operates from a wide 11v to 110v input range. the max5003 drives an external n- channel power mosfet and has a current-sense pin that detects overcurrent conditions and turns off the power switch when the current-limit threshold is exceeded. the choice of external power mosfet and other external components determines output voltage and power. the max5003 offers some distinctive advantages: soft- start, undervoltage lockout, external frequency synchro- nization, and fast input voltage feed-forward. the device is designed to operate at up to 300khz switch- ing frequency. this allows use of miniature magnetic components and low-profile capacitors. undervoltage lockout, soft-start, switching frequency, maximum duty cycle, and overcurrent protection limit are all adjustable using a minimum number of external components. in systems with multiple controllers, the max5003 can be externally synchronized to operate from a common sys- tem clock. warning: the max5003 is designed to operate with high voltages. exercise caution. the max5003 is available in 16-pin so and qsop pack- ages. an evaluation kit (max5003evkit) is also available. applications telecommunication power suppliesisdn power supplies +42v automobile systems high-voltage power-supply modules industrial power supplies features ? wide input range: 11v to 110v ? internal high-voltage startup circuit ? externally adjustable settings output switch current limitoscillator frequency soft-start undervoltage lockout maximum duty cycle ? low external component count ? external frequency synchronization ? primary or secondary regulation ? input feed-forward for fast line-transientresponse ? precision ?.5% reference over ratedtemperature range ? thermal shutdown max5003 high-voltage pwm power-supply controller ________________________________________________________________ maxim integrated products 1 1615 14 13 12 11 10 9 12 34 5 6 7 8 v+ v dd v cc ndrvpgnd cs agnd maxton fb top view max5003 qsop/narrow so indiv es ref freq ss con comp 19-1555; rev 2; 4/02 part max5003ceemax5003cse max5003eee -40? to +85? 0? to +70? 0? to +70? temp. range pin-package 16 qsop16 narrow so 16 qsop evaluation kit available note: dice are designed to operate over a -40? to +140? junc- tion temperature (t j ) range, but are tested and guaranteed at t a = +25?. pin configuration ordering information max5003ese -40? to +85? 16 narrow so max5003c/d (note a) dice for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. downloaded from: http:///
max5003 high-voltage pwm power-supply controller 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics(v+ = v es = v dd = +12v, v indiv = 2v, v con = 0, r freq = r maxton = 200k , t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v+ to gnd ............................................................-0.3v to +120v es to gnd ..............................................................-0.3v to +40v v dd to gnd ............................................................-0.3v to +19v v cc to gnd .........................................................-0.3v to +12.5v maxton, comp, cs, fb, con to gnd..................-0.3v to +8v ndrv, ss, freq to gnd ...........................-0.3v to (v cc + 0.3v) i ndiv , ref to gnd.................................................-0.3v to +4.5v v cc , v dd , v+, es current ................................................?0ma ndrv current, continuous...............................................?5ma ndrv current, 1? .............................................................?a con and ref current ......................................................?0ma all other pins ....................................................................?0ma continuous power dissipation (t a = +70?) 16-pin so (derate 9.5mw/? above +70?)...............762mw 16-pin qsop (derate 8.3mw/? above +70?)..........667mw maximum junction temperature (t j ) ..............................+150? operating temperature ranges max5003c_e ....................................................0? to +70? max5003e_e ..................................................-40? to +85? operating junction temperature (t j ) .............................+125? 16-pin so ja .................................................................105?/w 16-pin qsop ja ............................................................120?/w storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? i ref = 0 to 1ma no load v+ = v es , v dd = 18.75 i ndrv = 50 ma v indiv = 0, v+ = 110v, v es = v dd = unconnected i ndrv = 50 ma v ndrv = v cc v ndrv = 0, v cc supported by v cc capacitor v+ = 36v, es = unconnected, v dd = 18.75v v cc falling v+ = 36v, i v+ < 75?, es = unconnected v+ = v es = 36v, i ndrv = 7.5ma v+ = 110v, v dd = unconnected v+ = 36v, i dd = 0 to 7.5ma, es = unconnected mv 52 0 ? v ref ref voltage regulation v 2.905 3.000 3.098 v ref ref output voltage 1 r ol ndrv resistance low 41 2 r oh ndrv resistance high ma 1000 peak sink current ma 570 peak source current v 6.3 v cclo v cc undervoltage lockout voltage v cc v cc output voltage ma 1.2 i dd ? 35 75 i+ shutdown current supply current v 7.4 12 v 10.75 v to v dd regulator turn-off voltage v 10.75 18.75 v dd v dd input voltage range v 25 v 10.8 36 v esi e s input voltage (note 1) v 36 v eso e s output voltage v 9 9.75 10.5 v dd v dd output voltage conditions units min typ max symbol parameter v dd = unconnected, v+ = v es , i ndrv = 7.5ma v 110 v+ v+ input voltage (note 1) e s = v dd = uncon- nected reference output driver chip supply (v cc ) preregulator/startup supply current i ndrv = 2ma i ndrv = 5ma downloaded from: http:///
max5003 high-voltage pwm power-supply controller _______________________________________________________________________________________ 3 electrical characteristics (continued)(v+ = v es = v dd = +12v, v indiv = 2v, v con = 0, r freq = r maxton = 200k , t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 2) v freq = 5v, v con = 3.0v v con = 3.0v v con = 3.0v from end of blanking time 25mv overdrive 0 < v cs < 0.1v v indiv = 1.28v fb = comp, v con = 1.5v v+ = v es = v dd = 10.8v and 18.75v at comp at comp i comp = 5?; v comp = 0.5v, 2.5v r load = 200k , c load = 100pf a vol = 1v/v, c load = 100pf v fb = 1.5v khz 200 1200 f freq freq range ? 81 3 t ext external oscillator maximumlow time ? 1 i ol freq output low v 2.7 v ih freq input high v 0.8 v il freq input low ? -1 0.01 +1 indiv bias current mv 125 v hyst indiv hysteresis 1.23 1.32 1.45 v 1.15 1.20 1.25 v indivlo indiv undervoltage lockout ppm/? 100 tc fb fb v set tempco ? -1 0.1 +1 i fb fb bias current ns 70 t b cs blanking time ns 240 t d ? -1 +1 i cs cs input bias current overcurrent delay v 1.448 1.485 1.522 v set fb regulation voltage v 3.00 v comph output clamp high v 0.25 v compl output clamp low db 60 80 a v voltage gain mhz 1.2 bw unity-gain bandwidth degrees 65 phase margin f s = 1/4 f freq ns 150 freq hi/lo pulse width khz 50 300 f s frequency range conditions units min typ max symbol parameters v freq = 1.5v v freq = 0 ? 1 i ol freq output current low ? 300 i oh freq output current high khz 80 100 120 oscillator frequency k 50 500 r freq freq resistor range v indiv = 1.25v % 75 maximum programmable duty cycle v con = 1.25v mv 80 100 120 v cs cs threshold voltage maximum duty cycle (maxton) main oscillator?nternal mode main oscillator?xternal mode undervoltage lockout feedback input and set point error amplifier current limit v indiv falling v indiv rising downloaded from: http:///
0.8 -0.4-0.6 0 -0.2 0.60.4 0.2 0.8 0 -20 20 40 60 80 100 fb set-point voltage change vs. temperature max5003-01 temperature ( c) fb set-point voltage change (%) -0.100 -0.050-0.075 0 -0.025 0.0750.050 0.025 0.100 11 13 12 14 15 16 17 18 fb set-point voltage change vs. supply voltage max5003-02 v dd (v) fb set-point voltage change (%) -1.20 -0.80-1.00 -0.40-0.60 0.20 0 -0.20 0.40 -40 0 -20 20 40 60 80 100 switching frequency change vs. temperature max5003-03 temperature ( c) frequency change (%) typical operating characteristics (v dd = +12v, r freq = 200k , r maxton = 200k , t a = +25?, unless otherwise noted.) max5003 high-voltage pwm power-supply controller 4 _______________________________________________________________________________________ electrical characteristics (continued)(v+ = v es = v dd = +12v, v indiv = 2v, v con = 0, r freq = r maxton = 200k , t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) note 1: see the typical operating characteristics for preregulator current-to-voltage characteristics. note 2: maximum time freq can be held below v il and still remain in external mode. note 3: feed-forward ratio = duty cycle at (v indiv = 1.5v)/duty cycle at (v indiv = 1.875v) note 4: occurs at start-up and until v ref is valid. conditions units min typ max symbol parameters minimum on-time 200 ns ss source current v ss = 0.5v, v dd = unconnected, v con = 1.5v 3.4 5.5 9 ? ss sink current v ss = 0.4v (note 4) 10 ma ss time 0.45 s/? con bias current i con v con = 0.5v and 2.5v -1 0.01 1 ? r maxton = 200k , v indiv = 1.25v ? 7.5 t on maximum on-time range v indiv = 1.875v v 0.48 0.5 0.53 ramp voltage low v 2.5 ramp voltage high v indiv stepped from 1.5v to 1.875v, v con = 3.0v (note 3) 0.72 0.8 0.88 input voltage feed forwardratio k 50 500 r maxton maxton resistor range pwm comparator soft-start pwm oscillator thermal shutdown temperature 150 ? thermal hysteresis 20 ? thermal shutdown downloaded from: http:///
max5003 high-voltage pwm power-supply controller _______________________________________________________________________________________ 5 0 1.00.5 2.01.5 2.5 3.0 20 60 40 80 100 120 v+ input current vs. voltage max5003-04 v+ (v) i v + (ma) v con = v comp = v fb switching 0 0.50 1.00 2.001.50 2.50 -40 0 -20 20 40 60 80 100 v+ input current vs. temperature max5003-05 temperature (?) i v + (ma) v con = v comp = v fb switchingv+ = 110v max5003-06 0 2010 4030 7060 50 80 1.0 1.5 2.0 2.5 3.0 maximum duty cycle vs. v indiv v indiv (v) duty cycle (%) 400k parameter is r maxton 100k v con clamped high 300k 200k 70 -20 0.1k 1k 10k 100k 1m 10m error amp frequency response -10 0 max5003-07 frequency (hz) gain (db) 2010 50 6040 30 0-180 -160 -140 phase (degrees) -100-120 -40 -20-60 -80 phase gain max5003-08 0 100 50 200150 350300 250 400 0 100 200 300 400 500 switching frequency and period vs. r freq r freq (k ) frequency (khz) 0 10 20 30 40 period ( s) frequency period 30 3231 3433 38 37 3635 40 39 -40 0 -20 20 40 60 80 100 v+ shutdown current vs. temperature max5003-09 temperature (?) i v + ( a) v+ = 110vv indiv = 0 v dd = unconnected 28.027.5 27.0 26.5 26.0 -50 0 50 100 v+ current in bootstrapped operation vs. temperature max5003-10 temperature (?) i v + ( a) v+ = 110vv indiv = 1.5v 0 2 3 4 5 6 7 8 9 10 0 5 10 15 20 v cc load regulation max5003-11 i cc (ma) v cc (v) 1 v+ = 50v to 110v es = unconnectedv dd = unconnected v+ = 12v v+ = 13v v+ = 15v v+ = 14v typical operating characteristics (continued) (v dd = +12v, r freq = 200k , r maxton = 200k , t a = +25?, unless otherwise noted.) downloaded from: http:///
max5003 high-voltage pwm power-supply controller 6 _______________________________________________________________________________________ 0 2 3 4 5 6 7 8 9 10 0 5 10 15 20 v cc load regulation max5003-12 i cc (ma) v cc (v) 1 v+ = v es = 12v to 36v v dd = unconnected max5003-13 0 50 150100 300250 200 350 12 13 14 15 16 maximum frequency vs. input voltage and fet total gate-switching charge v+ (v) max switching frequency (khz) 25nc 30nc 10nc 15nc 20nc pin description typical operating characteristics (continued) (v dd = +12v, r freq = 200k , r maxton = 200k , t a = +25?, unless otherwise noted.) name function 1 v+ preregulator input. connect to the power line for use with 25v to 110v line voltages. bypass v+ to groundwith a 0.1? capacitor, close to the ic. connects internally to the drain of a depletion fet preregulator. 2 indiv undervoltage sensing and feed-forward input. connect to the center point of an external resistive dividerconnected between the main power line and agnd. undervoltage lockout takes over and shuts down the controller when v indiv < 1.2v. indiv bias is typically 0.01?. pin 3 es preregulator output. when v+ ranges above 36v, bypass es to agnd with a 0.1? capacitor close tothe ic. when v+ is always below 36v, connect es to v+. 4 freq oscillator frequency adjust and synchronization input. in internal free-running mode, the voltage on thispin is internally regulated to 1.25v. connect a resistor between this pin and agnd to set the pwm fre- quency. drive between v il and v ih at four times the desired frequency for external synchronization. 8 comp compensation connection. output of the error amplifier, available for compensation. 7 con control input of the pwm comparator 6 ref reference voltage output (3.0v). bypass to agnd with a 0.1? capacitor. 5 ss soft-start capacitor connection. ramp time to full current limit is approximately 0.5ms/nf. limits dutycycle when v ss < v con . 10 maxton maximum on-time programming. a resistor from maxton to agnd sets the pwm gain and limits themaximum duty cycle. the voltage on maxton tracks the voltage on the indiv pin. maximum on-time is proportional to the value of the programming resistor. the maximum duty cycle is limited to 75%, regard- less of the programming resistor. 9 fb feedback input. regulates to v fb = v ref / 2 = 1.5v. downloaded from: http:///
max5003 high-voltage pwm power-supply controller _______________________________________________________________________________________ 7 pin description (continued) name function pin 13 pgnd power ground. connect to agnd. 12 cs current sense with blanking. turns power switch off if v cs rises above 100mv (referenced to pgnd). connect a 100 resistor between cs and the current-sense resistor (figure 2). connect cs to pgnd if not used. 11 agnd analog ground. connect to pgnd close to the ic. 14 ndrv gate drive for external n-channel power fet 15 v cc output driver power-rail decoupling point. connect a capacitor to pgnd with half the value used forv dd bypass very close to the pin. if synchronizing several controllers, power the fan-out buffer driving the freq pins from this pin. 16 v dd 9.75v internal linear-regulator output. drive v dd to a voltage higher than 10.75v to bootstrap the chip supply. v dd is also the supply voltage rail for the chip. bypass to agnd with a 5? to 10? capacitor. detailed description the max5003 is a pwm controller designed for use asthe control and regulation core of voltage-mode control flyback converters or forward-voltage power convert- ers. it provides the power-supply designer with maxi- mum flexibility and ease of use. the device is specified up to 110v and will operate from as low as 11v. its maximum operating frequency of 300khz permits the use of miniature magnetic components to minimize board space. the range, polarity, and range of output voltages and power are limited only by design and by the external components used. this device works in isolated and nonisolated configu- rations, and in applications with single or multiple out- put voltages. all the building blocks of a pwm voltage-mode controller are present in the max5003 and its settings are adjustable. the functional diagram is shown on figure 1. modern voltage-mode controllers the max5003 offers a voltage-mode control topologyand adds features such as fast input voltage feed for- ward, programmable maximum duty cycle, and high operating frequencies. it has all the advantages of cur- rent-mode control?ood control loop bandwidth, same-cycle response to input voltage changes, and pulse-by-pulse current limiting. it eliminates disadvan- tages such as the need for ramp compensation, noise sensitivity, and the analytical and design difficulties of dealing with two nested feedback loops. in summary, voltage-mode control has inherent superior noise immunity and uses simpler compensation schemes. internal power regulators the max5003? power stages operate over a widerange of supply voltages while maintaining low power consumption. for the high end of the range (+36v to +110v), power is fed to the v+ pin into a depletion junction fet preregulator. this input must be decou- pled with a 0.1? capacitor to the power ground pin (pgnd). to decouple the power line, other large-value capacitors must be placed next to the power trans- former connection. the preregulator drops the input voltage to a level low enough to feed a first low-dropout regulator (ldo) (figure 1). the input to the ldo is brought out at the es pin. es must also be decoupled with a 0.1? capacitor. in applications where the maximum input voltage is below 36v, connect es and v+ together and decouple with a 0.1? capacitor. the first ldo generates the power for the v dd line. the v dd line is available at the v dd pin for decoupling. the bypass to agnd must be a 5? to 10? capacitor.when the maximum input voltage is always below 18.75v, power may also be supplied at v dd ; in this case, connect v+, es, and v dd together. forcing voltages at v dd above 10.75v (see electrical characteristics ) disables the first ldo, typically reduc- ing current consumption below 50? (see typical operating characteristics ). following the v dd ldo is another regulator that drives v cc : the power bus for the internal logic, analog cir- cuitry, and external power mosfet driver. this regula-tor is needed because the v dd voltage level would be too high for the external n-channel mosfet gate. the downloaded from: http:///
max5003 high-voltage pwm power-supply controller 8 _______________________________________________________________________________________ freqrefok sdn indiv maxton ramp agnd v cc v cc clk ramp v cc rr v ref cs blank driver ndrv currentsense c limit refrefok v in ok v in ok bandgap reference linear regulator v cc ok v dd v dd v cc v cc sdn agnd agnd linear regulator v dd v es agnd 100ns stretching v cc v cc pgnd 1615 14 13 12 11 10 9 v dd 12 1.2v 3 uv lockout 45 6 7 v+ indiv es freq ss ref con comp 8 v cc ndrvpgnd cs agnd maxton fb v cc pgnd agnd high-voltage epifet v fetbias v cc pgnd 0.1v pwm comp ss sdn error amp v con agnd agnd clk q d ??f max5003 r ? figure 1. functional diagram downloaded from: http:///
v cc regulator has a lockout line that shorts the n-chan- nel mosfet driver output to ground if the v cc ldo is not regulating. v cc feeds all circuits except the v cc lockout logic, the undervoltage lockout, and the powerregulators. the preferred method for powering the max5003 is to start with the high-voltage power source (at v+ or es, depending on the application), then use a bootstrap source from the same converter with an output voltage higher than the v dd regulator turn-off voltage (10.75v) to power v dd . this will disable the power consumption of the v dd ldo. it is also possible to power the max5003 with no bootstrap source from es or v+, butdo not exceed the maximum allowable power dissipa- tion. the current consumption of the part is mostly a function of the operating frequency and the type of external power switch used?n particular, the total charge to be supplied to the gate. a reference output of 3v nominal is externally available at the ref pin, with a current sourcing capability of 1ma. a lockout circuit shuts off the oscillator and the output driver if ref falls 200mv below its set value. minimize loading at ref, since the ref voltage is the source for the fb voltage, which is the regulator set point when the error amplifier is used. any changes in v ref will be proportionally reflected in the regulated output voltage of the converter. undervoltage lockout, feed forward, and shutdown the undervoltage lockout feature disables the controllerwhen the voltage at indiv is below 1.2v (120mv hys- teresis). when indiv rises higher than 1.2v plus the hysteresis (typically 1.32v), it allows the controller to start. an external resistive divider connected between the power line and agnd generates the indiv signal. indiv is also used as the signal for the fast input volt- age feed-forward circuit. always connect indiv to a voltage divider. it is not a ?on? care?condition; the signal is used to set the fast feed-forward circuit (see the oscillator and ramp generator section). choose r2 (figure 2) between 25k to 500k and cal- culate r1 to satisfy the following equation:where v sul = system undervoltage lockout and v indivlo = i ndiv undervoltage lockout. the undervoltage lockout function allows the use of theindiv pin as a shutdown pin with an external switch to ground. the shutdown circuit must not affect the resis-tive divider during normal operation. current-sense comparator the current-sense (cs) comparator and its associatedlogic limit the current through the power switch. current is sensed at cs as a voltage across a sense resistor between the external mosfet source and pgnd. connect cs to the external mosfet source through a 100 resistor or rc lowpass filter (figures 2 and 3). see cs resistor in the component selection section. a blanking circuit shunts cs to ground when the powermosfet switch is turned off, and keeps it there for 70ns after turn-on. this avoids false trips caused by the switching transients. the blanking circuit also resets the rc filter, if used. when v cs > 100mv, the power mosfet is switched off. the propagation delay fromthe time the switch current reaches the trip level to the driver turn-off time is 240ns. if the current limit is not used, the cs pin must be connected to pgnd. error amplifier the internal error amplifier is one of the building blocksthat gives the max5003 its flexibility. its noninverting input is biased at 1.5v, derived from the internal 3v ref- erence. the inverting input is brought outside (fb pin) and is the regulation feedback connection point. if the error amplifier is not used, connect this pin to ground. the output is available for the frequency compensation network and for connection to the input of the pwm comparator (con). unity-gain frequency is 1.2mhz, open-circuit gain is 80db, and the amplifier is unity- gain stable. to eliminate long overload recovery times, there are clamps limiting the output excursions close to the range limits of the pwm ramp. the voltage at the noninverting input of the error amplifier is the regulator set point, but is not accessible. set-point voltage can be measured, if needed, by con- necting comp and fb and measuring that node with respect to ground. the error amplifier is powered from the v cc rail. pwm comparator the pulse-width modulator (pwm) comparator stagetransforms the error signal into a duty cycle by comparing the error signal with a linear ramp. the ramp levels are 0.5v min and 2.5v max. the comparator has a typical hysteresis of 5.6mv and a propagation delay of 100ns. the output of the comparator controls the external fet. soft-start the soft-start feature allows converters built using themax5003 to apply power to the load in a controllable soft ramp, thus reducing start-up surges and stresses. rr v v sul indivlo 12 1 - = ? ? ? ? ? ? max5003 high-voltage pwm power-supply controller _______________________________________________________________________________________ 9 downloaded from: http:///
max5003 it also determines power-up sequencing when severalconverters are used. upon power turn-on, the ss pin acts as a current sink to reset any capacitance attached to it. once ref has exceeded its lockout value, ss sources a current to the external capacitor, allowing the converter output volt- age to ramp up. full output voltage is reached in approximately 0.45s/?. the ss pin is an overriding extra input to the pwm comparator. as long as its voltage is lower than v con , it overrides v con and ss determines the level at which the duty cycle is decided by the pwm comparator.after exceeding v con , ss no longer controls the duty cycle. its voltage will keep rising up to v cc . oscillator and ramp generator the max5003 oscillator generates the ramp used bythe comparator, which in turn generates the pwm digi- tal signal. it also controls the maximum on-time feature of the controller. the oscillator can operate in two modes: free running and synchronized (sync). a single pin, freq, doubles as the attachment point for the fre- quency programming resistor and as the synchroniza- tion input. the mode recognition is automatic, based on the voltage level at the freq pin. in free-running mode, a 1.25v source is internally applied to the pin; the oscillator frequency is propor- tional to the current out of the pin through the program- ming resistor, with a proportionality constant of 16khz/?. in sync mode, the signal from the external master gen- erator must be a digital rectangular waveform running at four times the desired converter switching frequency. minimum acceptable signal pulse width is 150ns, posi- tive or negative, and the maximum frequency is 1.2mhz. when the voltage at freq is forced above 2.7v, the oscillator goes into sync mode. if left at or below 1.5v for more than 8? to 20?, it enters free-running mode. the master clock generator cannot be allowed to stop at logic zero. if the system design forces such a situa- tion, an inverter must be used at the freq pin. in sync mode, the oscillator signal is divided by four and decoded. the output driver is blocked during the last phase of the division cycle, giving a hardwired maximum on-time of 75%. in free-running mode, the oscillator duty cycle is 75% on, and the off portion also blocks the out- put driver. the maximum on-time is then absolutely limit- ed to 75% in either mode. maximum on-time can be controlled to values lower than 75% by a programming resistor at the maxton pin. the pwm ramp generated goes from 0.5v min to 2.5vmax, and the maximum time on is the time it takes from low to high. maxton is internally driven to v indiv and a resistor must be connected from maxton to agnd, to pro-gram the maximum on-time. the ramp slope is directly proportional to v indiv and inversely proportional to r maxton . since the ramp volt- age limits are fixed, controlling the ramp slope sets themaximum time on. changing the ramp slope while v con remains constant also changes the duty cycle and the energy transferred tothe load per cycle of the converter. the indiv signal is a fraction of the input voltage, so the fast input voltage feed- forward works by modifying the duty cycle in the same clock period, in response to an input voltage change. calculate the maximum duty cycle as: where: d max = maximum duty cycle (%) maxton = maximum on-timet = switching period then: where: r maxton = resistor from the maxton pin to ground v indiv = voltage at the indiv pin sw = output switching frequency maxton can then be calculated as: n-channel mosfet output switch driver the max5003 output drives an n-channel mosfettransistor. the output sources and sinks relatively large currents, supplying the gate with the charge the tran- sistor needs to switch. these are current spikes only, since after the switching transient is completed the load is a high-value resistance. the current is supplied from the v cc rail and must be sourced by a large-value maxton rv k v khz maxton indiv = ? 075 125 200 100 . . d 0.75 100 r 200k 1.25v v 100khz max maxton indiv sw = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? d maxton t max = 100 high-voltage pwm power-supply controller 10 ______________________________________________________________________________________ downloaded from: http:///
capacitor (5? to 10?) at the v cc pin, since the rail will not support such a load. it is this current, equivalent tothe product of the total gate switching charge (from the n-channel mosfet data sheet), times the operating frequency, that determines the bulk of the max5003 power dissipation. the driver can source up to 560ma and sink up to 1a transient current with a typical on source resistance of 4 . the no-load output levels are v cc and pgnd. applications information compensation and loop design considerations the circuit shown in figure 2 is essentially an energypump. it stores energy in the magnetic core and the air gap of the transformer while the power switch is on, and delivers it to the load during the off phase. it can operate in two modes: continuous and discontinuous. in discontinuous mode, all the energy is given to the load before the next cycle begins; in continuous mode, some energy is continuously stored in the core. the system has four operating parameters: input volt- age, output voltage, load current, and duty cycle. the pwm controller senses the output voltage and the input voltage, and keeps the output voltage regulated by controlling the duty cycle. the output filter in this circuit consists of the load resis- tance and the capacitance on the output. to study the stability of the feedback system and design the compensation necessary for system stability under all operating conditions, first determine the trans- fer function. in discontinuous mode, since there is no energy stored in the inductor at the end of the cycle, the inductor and capacitor do not show the characteris- tic double pole, and there is only a dominant pole defined by the filter capacitor and the load resistance. there is a zero at a higher frequency, defined by the esr of the output filter capacitor. such a response is easy to stabilize for a wide range of operating condi- tions while retaining a reasonably fast loop response. in continuous mode, the situation is different. the inductor-capacitor combination creates a double pole, since energy is stored in the inductor at all times. in addition to the double pole, a right-half-plane zero appears in the frequency response curves. this response is not easy to compensate. it can result in conditional stability, a complicated compensation net- work, or very slow transient response. to avoid the analytical and design problems of the con- tinuous-conduction mode flyback topology and maintain good loop response, choose a design incorporating adiscontinuous-conduction mode power stage to keep the converter in discontinuous mode at all times, the value of the power transformer? primary inductance must be calculated at minimum line voltage and maxi- mum load, and the maximum duty cycle must be limited. the max5003 has a programmable duty-cycle limit func- tion intended for this purpose. design methodology following is a general procedure for developing a sys-tem: 1) determine the requirements. 2) in free-running mode, choose the freq pin pro- gramming resistor. in synchronized mode, determinethe clock frequency (f clk) . 3) determine the transformer turns ratio, and check the maximum duty cycle. 4) determine the transformer primary inductance. 5) complete the transformer specifications by listing the primary maximum current, the secondary maxi-mum current, and the minimum duty cycle at full power. 6) choose the maxton pin programming resistor. 7) choose a filter capacitor. 8) determine the compensation network. design example 1) 36v < v in < 72v, v out = 5v, i out = 1a, ripple < 50mv, settling time 0.5ms. 2) generally, the higher the frequency, the smaller the transformer. a higher frequency also gives highersystem bandwidth and faster settling time. the trade-off is lower efficiency. in this example, 300khz switching frequency is the choice to favor for a small transformer. if the converter will be free running (not externally synchronized), use the following formula to calculate the r freq programming resistor: where:r freq = resistor between freq and ground sw = switching frequency (300khz) if the converter is synchronized to an external clock,the input frequency will be 1.2mhz. the external clock runs at four times the desired switching fre- quency. r khz kk freq sw = ? ?? ? ?? ? = 100 200 66 7 . max5003 high-voltage pwm power-supply controller ______________________________________________________________________________________ 11 downloaded from: http:///
max5003 3) the main factors influencing the choice of the turns ratio are the switch breakdown voltage and the dutycycle. with a smaller turns ratio, the secondary reflected voltage and the maximum voltage seen by the switch during flyback are reduced, which is favorable. on the other hand, a smaller turns ratio will shorten the duty cycle and increase the primary rms current, which can impact efficiency. a good starting figure is the ratio of the input voltage to the output voltage, rounding to the nearest integer. to keep the flyback voltage under control, choose an 8- to-1 ratio for the 48v to 5v system. the maximum duty cycle allowed without putting the device in con- tinuous-conduction mode can be found using the fol- lowing formula: where: n = n p /n s = turns ratio v sec = secondary voltage dc max = maximum duty cycle v min = minimum power-line voltage for a 48v to 5v system with an 8-to-1 turns ratio, themaximum duty cycle before putting the device in discontinuous mode is 55%. assume that v in min is 36v (minimum input voltage, neglecting drops in thepower switch and in the resistance of the primary coil) and v sec is 5.4v (5v plus a schottky diode drop). the max5003 maximum duty cycle is internal-ly limited to 75%. generally this parameter must fall between 45% to 65% to obtain a balance between efficiency and flyback voltage while staying out of continuous conduction. if the value exceeds these bounds, adjust the turns ratio. 4) assuming 80% efficiency, a 6.25w input is needed to produce a 5w output. set an operating duty cyclearound 12% below the maximum duty cycle to allow for component variation: 55% - 12% = 43%. use the following formula to calculate the primary inductance: l dc v pwr v w khz h pri min in sw = () ? = () ? 22 2 043 36 2 6 25 300 65 . . dc v vn max min sec = ?? ? ?? ? + 1 1 high-voltage pwm power-supply controller 12 ______________________________________________________________________________________ 10 f 0.1 f c f 390pf 0.1 f 0.1 f 0v 470nf r f 200k r cs 0.1 51k 62k v+indiv es freq ss ref con comp 8 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 v dd v cc ndrv pgnd cs agnd cmsd4448 xfacoiltrctx03 mbrs130l 8 25 7 9, 10 11, 12 irfd620s maxton fb 39k 1m 33 f 0.1 f 100 +5v 1a +48v (36v to 72v) v in r a 41.2kr b 17.4k 22 f 4.7 f l p 65 h 22 f max5003 figure 2. application example 1: nonisolated +48v to +5v converter downloaded from: http:///
where: dc = duty cycle. set to calculated minimum duty cycle at v min. pwr in = input power, at maximum output power this gives an inductance value (l pri ) of approxi- mately 65?. 5) the other parameter that defines the transformer is peak current. this is given by:the peak secondary current is the peak primary cur- rent multiplied by the turns ratio, or 0.8a 8 = 6.4a. calculating the minimum duty cycle:with these numbers, the transformer manufacturer can choose a core. 6) for this application, the max5003 must be pro- grammed for a maximum duty cycle of 55% at 36v.the max5003 will automatically scale the limit with the reciprocal of the input voltage as it changes. the duty-cycle limit for an input voltage of 72v will be 27% (half of 55%). the duty cycle needed to stay out of continuous conduction at 72v is 37%, so there is a 10% margin. the maximum duty time scales with the voltage at the undervoltage lockout pin, v indiv . the voltage at indiv is set by selecting the power lineundervoltage lockout trip point. the trip point for this system, running from 36v to 72v, is 32v. then indiv must be connected to the center point of a divider with a ratio of 32/1.25, connected between the power line and ground. then r maxton is: r v v khz dc v k vv khz khz kk maxton min uvl sw max min = ?? ? ?? ? ? ?? ? ?? ? () ?? ? ?? ? = ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? = % % % 100 75 200 3632 100 300 55 75 200 55 ? dc dc v v v v min max in min in max () ( ) () () % = = = 43 36 72 i 2 pwr l 2 6.25w 65 h 300khz 0.8a pri in pri sw = ? == max5003 high-voltage pwm power-supply controller ______________________________________________________________________________________ 13 10 f 0.1 f 51k 1.3k r cs 0.1 0.1 f 0.1 f 470nf 62k v+indiv es freq ss ref con comp 8 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 v dd v cc ndrv pgnd cs agnd mdc217 irfd620s l p 65 h maxton fb r2 39k r11m 33 f 0.1 f 100 +5v1a - 51 680 240k 6 7 5 2 1 22 f 0.01 f 3900pf 24.9k 24.9k tl431 4.7 f 22 f max5003 v in 0v xfacoiltrctx03 cmsd4448 mbrs130l 8 2 5 7 9, 10 11, 12 -48v -36v to -72v figure 3. application example 2: isolated -48v to +5v converter downloaded from: http:///
max5003 where:r maxton = resistor between the maxton pin and ground v min = minimum power-line voltage v uvl = power-line trip voltage dc max (v min ) = maximum duty cycle at minimum power-line voltage for this application circuit, a 10% margin is reason-able, so the value used is 50k . this gives a maxi- mum duty cycle of 50%. the maximum duty cyclecan now be expressed as: where: v con = voltage at the con pin, input of the pwm comparator dc(v con , v in ) = duty cycle, function of v con and v in 0.5v and 2.5v are the values at the beginning andend of the pwm ramp. the term sw / nom varies from 0.8 to 1.2 to allow for clock frequency variation. if the clock is runningat 300khz and the input voltage is fixed, then the duty cycle is a scaled portion of the maximum duty cycle, determined by v con . 7) low-esr/esl ceramic capacitors were used in this application. the output filter is made by two 22?ceramic capacitors in parallel. normally, the esr of a capacitor is a dominant factor determining the rip- ple, but in this case it is the capacitor value. calculating the ripple will be a fraction of this depending on theduty cycle. for a 50% duty cycle, the ripple due to the capacitance is approximately 45mv. 8)the pwm gain can be calculated from: note that while the above formula incorporates theproduct of the maximum duty cycle and v in , it is independent of v in . for 1a output (r l = 5 ), the pwm gain is +3.0v/v. for a 10% load (r l = 50 ), the gain is multiplied by the square root of 10 andbecomes +10v/v. the pole of the system due to the output filter is 1 / 2 rc, where r is the load resis- tance and c the filter capacitor. choosing a capaci-tor and calculating the pole frequency by: it is 723hz at full load. at 10% load it will be 72hz, since the load resistor is then 50 instead of 5 . the total loop gain is equal to the pwm gain times thegain in the combination of the voltage divider and the error amplifier. the worst case for phase margin is at full load. for a phase margin of 60 degrees, this midband gain (g) must be set to be less than: where: u = unity-gain frequency of error amplifier pm = phase margin angle the dc accuracy of the regulator is a function of thedc gain. for 1% accuracy, a dc gain of 20 is required. since the maximum midband gain for a stable response is 16, an integrator with a flat midband gain given by a zero is used. the midband gain is less than 16, to preserve stability, and the dc gain is much larger than 20, to achieve high dc accuracy. optimization on the bench showed that a midband gain of 5 gave fast transient response and settling with no ringing. the zero was pushed as high in frequency as possible without losing stability. the zero must be a factor of two or so below the system unity-gain frequen- cy (crossover frequency) at minimum load. with the g pm a mhz hz uerroramp pwm p tan( ) . < ? ? = 1 1 7 3 723 ?= ?? ? ?? ? = ?? ? ?? ? p ll rc f 1 2 1 2544 a dv dv r 2l v 2.0v r 2l pwm out con l pri sw min l pri sw == ? ?? ? ?? ? = ? ?? ? ?? ? ? . % ( dc v v max vm i 36 20 50 3 i c a khz f mv out sw ? = = 1 300 44 76 dc(v ,v ) = v - 0.5v 2.0v 50% dc(v ,v ) v - 0.5v 2.0v 25% dc(2.5v,v ) 50% dc(2.5v,v ) 25% dc(0.5v,v ) 0 dc(0.5v,v ) 0 con min con con max con minmax min max ?? ? ?? ? = ?? ? ?? ? = = = = dc(v ) v - 0.5v 2.0v v v dc v - 0.5v 2.0v 36v v 50% con,vin con min in nom max(vmin) con in sw nom = ?? ? ?? ? ?? ? ?? ? ? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ? ? ?? ? ?? ? sw high-voltage pwm power-supply controller 14 ______________________________________________________________________________________ downloaded from: http:///
zero at 2khz, the crossover frequency is 4khz and thephase margin is 50? given the above considerations, r a , r b , r f , and c f can be chosen (figure 2). the sum of r a and r b is chosen for low current drain. in the example, r a plus r b is 58k and draws 80?. the following ratio sets the output voltage: r b / (r a + r b ) = v set / v out since v set = 1.5v and v out = 5v, r a is set to 41.2k and r b to 17.4k . the midband gain is the ratio of r f /r a . r b does not affect the gain because it is connected to a virtualground. for a midband gain of 5, the feedback resistor equals 200k . to set the zero at 2khz, the capacitor value is: c f = 1 / (2 x r f x f z ) = 400pf layout recommendations all connections carrying pulsed currents must be veryshort, be as wide as possible, and have a ground plane behind them whenever possible. the inductance of these connections must be kept to an absolute mini- mum due to the high di/dt of the currents in high- frequency switching power converters. in the develop- ment or prototyping process, multipurpose boards, wire wrap, and similar constructive practices are not suit- able for these type of circuits; attempts to use them will fail. instead, use milled pc boards with a ground plane, or equivalent techniques current loops must be analyzed in any layout pro- posed, and the internal area kept to a minimum to reduce radiated emi. the use of automatic routers is discouraged for pc board layout generation in the board area where the high-frequency switching con- verters are located. designers should carefully review the layout. in particular, pay attention to the ground connections. ground planes must be kept as intact as possible. the ground for the power-line filter capacitor and the ground return of the power switch or current- sensing resistor must be close. all ground connections must resemble a star system as much as practical. ?hort?and ?lose?are dimensions on the order of 0.25in to 0.5in (0.5cm to about 1cm). setting the output voltage the output voltage of the converter, if using the internalerror amplifier, can easily be set by the value of the fb pin set voltage. this value is 1.5v. a resistive divider must be calculated from the output line to ground, with a dividing ratio such that when the output is at the desired value, the center-point voltage will be 1.5v. thethevenin equivalent of the resistors must be low enough so the error amplifier bias current will not intro- duce a division error. the two resistors must have simi- lar temperature coefficients (tempcos), so the dividing ratio will be constant with temperature. component selection cs resistor the cs resistor is connected in series with the sourceof the n-channel mosfet and ground, sensing the switch current. its value can be calculated from the fol- lowing equation: where = efficiency and 0.5 < kt ol < 0.75. k tol includes the tolerance of the sensing resistor, the dispersion of the max5003 cs trip point, and theuncertainties in the calculation of the primary maximum current. the sensing resistor must be of the adequate power dissipation and low tempco. it must also be noninduc- tive and physically short. use standard surface-mount cs resistors. a 100 resistor is recommended between the cs resistor and the cs pin. if the current surge atthe beginning of the conduction period is large and dis- rupts the max5003 s operation, add a capacitor between the cs pin and pgnd, to form an rc filter. power switch the max5003 will typically drive an n-channel mosfetpower switch. the maximum drain voltage, maximum r ds(on) , and total gate switching charge are the para- meters involved in choosing the fet. the maximumgate switching charge is the most important factor defining the max5003 internal power consumption, since the product of the switching frequency and the total gate charge is the ic current consumption. r ds(on) is the parameter that determines the total con- duction power losses in the switch, and the choicedepends on the expected efficiency and the cooling and mounting method. the maximum drain voltage requirements can be different depending on the topolo- gy used. in the flyback configuration, the maximum voltage is the maximum supply voltage plus the reflect- ed secondary voltage, any ringing at the end of the conduction period, and the spike caused by the leak- age inductance. in the case of the forward converter, the reset time of the core will set the maximum voltage r mv i mv pwr l k cs lim pri out max pri sw tol () () == ? 100 100 2 max5003 high-voltage pwm power-supply controller ______________________________________________________________________________________ 15 downloaded from: http:///
stress on the switch. a fet with the lowest total chargeand the lowest r ds(on ) for the maximum drain voltage expected (plus some safety factor) is the best choice.the choice of package is a function of the application, the total power, and the cooling methods available. transformer transformer parameters, once calculated in the designprocess, can be used to find standard parts whenever possible. the most important factors are the saturation current, primary inductance, leakage inductance turns ratio, and losses. packaging and emi generation and susceptibility are closely connected, and must be con- sidered. in general, parts with exposed air gaps (not contained inside the magnetic structure) will generate the most radiated emi, and might need external shield- ing. if the design is in high-voltage power supplies, the insulation specifications are also important. pay close attention if the circuitry is galvanically connected to the mains at any point, since serious safety and regulatory issues might exist. capacitors as in any high-frequency p ower circuit, the capacitors used for filtering must meet very low esr and eslrequirements. at the 300khz frequency (of which the max5003 is capable), the most favorable technologies are ceramic capacitors and organic semiconductor (os con) capacitors. the temperature dependence of the capacitance value and the esr specification is important, particularly if the esr is used as part of the compensation network for the feedback loop. if using through-hole- mounted parts, keep lead length as short as practical.components with specifications for switching power con- verters are preferred. decoupling capacitors must be mounted close to the ic. diodes the choice of rectifier diodes depends on the outputvoltage range of the particular application. for low-volt- age converters, the diode drop is a significant portion of the total loss, and must be kept to a minimum. in those cases, schottky diodes are the preferred compo- nent for the design. at higher voltages, ultra-fast recov- ery diodes must be used, since schottky components will not satisfy the reverse voltage specification. for all cases, the specifications to be determined before choosing a diode are the peak current, the aver- age current, the maximum reverse voltage, and the maximum acceptable rectification losses. once a type is identified, a thermal analysis of the diode losses vs. total thermal resistance (from junction to ambient) must be carried out if the total power involved is significant. industrial-frequency (60hz) rectifiers are not recom- mended for any function in these converters, due to their high capacitance and recovery losses. if using overdimensioned rectifiers, the junction capacitance influence must be reviewed. max5003 high-voltage pwm power-supply controller maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. ___________________chip information transistor count: 1050substrate connected to gnd manufacturer phone device type current-sense resistors dale-vishay 402-564-3131 power fets fairchild 408-822-2000 international rectifier 310-322-3333 motorola 303-675-2140 diodes central semiconductor 516-435-1110 transistors central semiconductor 516-435-1110 fax 402-563-6418 408-822-2102 310-322-3332 303-675-2150 516-435-1824 516-435-1824 capacitors sanyo 619-661-6835 619-661-1055 taiyo yuden 408-573-4150 408-573-4159 avx 803-946-0690 803-626-3123 coils coiltronics 561-241-7876 561-241-9339 table 1. component manufacturers downloaded from: http:///

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